News: Microelectronics
22 June 2026
ASML, TSMC and imec present 300mm integration route for industry-ready 2D-material-based transistors
In partnership with equipment provider Advanced Semiconductor Materials Lithography (ASML) of Veldhoven, The Netherlands and foundry Taiwan Semiconductor Manufacturing Corp (TSMC), nanoelectronics research center imec of Leuven, Belgium has presented a novel, robust and scalable 300mm integration route for 2D-material-based nFETs and pFETs at the 2026 IEEE/JSAP Symposium on VLSI Technology & Circuits in Honolulu, Hawaii, USA (14–18 June).
For the first time, scaled nFETs (implementing MoS2 as the channel material) and pFETs (either WS2- or WSe2-based) with 50nm contacted poly pitch (CPP) could be demonstrated, with good current–voltage characteristics. imec says that these results represent a crucial step in the lab-to-fab transition of 2D-material based transistors, which are envisioned for further extending and augmenting the technology roadmap for ultra-scaled logic as well as for back-end and wafer backside applications.
Figure 1 - (A) X-cut HAADF STEM for a WS2 device with a CPP of 50nm, a contact length of 19nm and width of 256nm, after gate connection line etch. (B) Corresponding energy-dispersive x-ray spectroscopy (EDS) analysis.
2D transition-metal dichalcogenides (TMDs, such as MoS2, WS2 and WSe2) have the potential to extend and augment the logic scaling technology roadmap. When integrated as atomically thin conduction channels replacing silicon, these materials enable high-performance scaled transistors – attractive for ultra-scaled logic as well as for back-end-of-line and wafer backside applications. They owe this promise to their good electrostatic channel control while maintaining acceptable carrier mobilities, even at ultra-scaled gate and channel lengths. But the path to industrial adoption has so far been hampered by the lack of a 300mm integration route that can offer TMD-based n and pFETs at industry-relevant dimensions, while preserving the performance that has extensively been demonstrated on a lab scale.
ASML, TSMC and imec and now present a scalable, back-end-compatible 300mm integration approach for TMD-based nFETs and pFETs, which has led to three key outcomes:
(1) scaled nFETs and pFETs with 50nm contacted poly pitch (CPP) — a world first;
(2) very low off-current (Ioff) at zero gate voltage (Vg=0V) for both transistor polarities; and
(3) pFETs with WSe2 channel performing close to record lab-based devices.
With 94% operational transistors (i.e. with Imax/Imin >105), the CMOS-like integration approach — with nFETs and pFETs integrated on the same 300mm wafer — is proven to be robust and stable. The proposed process flow is applicable to 2D channel materials other than MoS2, WS2 and WSe2.
“Transistors based on 2D TMD materials are typically optimized for small channel lengths. However, they usually have a large contact area to keep the contact resistance as low as possible, hindering further scaling,” says Gouri Sankar Kar, VP R&D compute and memory device technologies at imec. “For the first time, we achieved 50nm CPP — a metric determined by both the gate length and source/drain contact length — without affecting the performance of the 2D nFETs and pFETs. The use of single-patterning EUV lithography, optimized in close collaboration with ASML, was key in enabling the scaled CPP.”
Figure 2 – MoS2 nFETs and WSe2 pFETs with 50nm contact pitch and relaxed channel width (650nm), integrated on the same 300mm wafer, show proper threshold voltage matching.
The scaled transistors show good current–voltage characteristics, with pFETs performing nearly as well as the best-performing lab-based devices — addressing a long-standing challenge for TMD transistors. In addition, electrical results show that both transistor polarities turn off when the gate voltage (Vg) is set to 0V. “This ideal behavior can be ascribed to the use of an innovative ‘reverse’ thin-film transistor (TFT) fabrication flow,” explains Gouri Sankar Kar. “Unlike conventional 2D-material-based transistors, our n and pFETs have bottom contacts and an overlapping deposited gate. This is realized by transferring the TMD channel material onto already pre-patterned tungsten (W)-filled trenches working as the contacts,” he adds.
“Our research collaboration is instrumental in pushing the boundaries of semiconductor innovation,” says TSMC’s VP & chief technology officer Dr Min Cao, highlighting the strategic importance of the research work. “The focus is on de-risking and accelerating the ‘lab to fab’ transition, ensuring that groundbreaking discoveries — especially in these novel channel materials — could be rapidly and efficiently integrated into advanced manufacturing, and ultimately deliver cutting-edge solutions,” he adds.
“2D TMD materials could potentially enable much smaller and higher-performance transistors than those based on silicon, but 2D-channel devices that have been demonstrated so far using 300mm processes are actually fairly large, and patterned using older lithographic technologies,” says Etienne De Poortere, director of ASML’s Technology Development Center Europe. “Thanks to the much sharper resolution of EUV lithography, we were able to create TMD transistors with channel lengths as small as 28nm, and at a pitch compatible with the most advanced transistor nodes.”
“Together with our partners we have enabled a 300mm test platform to study 2D materials at industry relevant dimensions,” notes Gouri Sankar Kar. “We invite collaborations from the semiconductor ecosystem to drive performance for this new class of channel materials and devices.”
Imec presents record WSe2-based 2D-pFETs for extending logic technology roadmap
