News: Optoelectronics
4 August 2026
Palomino completes acquisition of Vega Links
Artificial intelligence (AI) interconnect technology company Palomino Laboratories Inc of Goleta, CA, USA has closed its acquisition of Vega Links Inc, creating a next-generation AI interconnect company.
Palomino is developing next-generation connectivity solutions for the rapidly evolving AI infrastructure market. The product focus addresses AI interconnect solutions in the 0–50m range and includes: (i) silicon chipsets enhancing the speed of copper, (ii) silicon optical integrated circuits (IC’s) optimizing the performance of micro-VCSEL interconnects, and (iii) silicon and gallium nitride ICs for micro-LED interconnects. Chipsets are designed to enable high-bandwidth, low-latency, and energy-efficient data movement across AI systems. Solutions are designed to support the growing performance demands of AI, high-performance computing (HPC), enterprise networking, hyperscale data centers and advanced robotics, as increasingly intelligent systems require faster, more efficient, and more reliable data connectivity.
Vega Links was founded to pioneer advanced AI systems architecture and interconnect technologies for next-generation AI infrastructure, bringing expertise in high-speed AI and memory connectivity. The acquisition accelerates Palomino’s strategy to become a leading AI interconnect technology company, combining its gallium nitride (GaN) micro-LED technologies with Vega Links’ silicon design, systems architecture, and product engineering strengths.
Executive leadership and Strategic Advisory Board actions
Palomino’s has appointed Karthik Gopalakrishnan as chief technology officer (CTO) and Rajesh Radhamohan as chief product officer (CPO).
It has also appointed Sudeep Bhoja and Gopal Raghavan to its Strategic Advisory Board.
Picture: Karthik Gopalakrishnan appointed CTO and Rajesh Radhamohan as CPO; Sudeep Bhoja and Dr Gopal Raghavan join Palomino’s Strategic Advisory Board.
Bhoja is co-founder & CTO of d-Matrix, an AI computing company building next-generation inference accelerators for generative AI. He has more than 25 years of experience in semiconductor architecture, high-speed interconnects, and AI computing. Previously, he was CTO of the Datacenter business unit at Inphi Corp (acquired by Marvell Technology), where he led the development of PAM4 DSP interconnect and silicon photonics technologies. Previously, he was technical director in Broadcom’s Infrastructure and Networking Group, with earlier roles at Lucent Technologies and Texas Instruments.
Raghavan is a veteran Silicon Valley semiconductor executive, entrepreneur and technology strategist with more than four decades of leadership spanning semiconductor architecture, embedded AI, and high-performance computing. He has held executive leadership and technical roles at Microsoft, Renesas Electronics, Cadence Design Systems, Intel, Hughes Electronics, and Conexant, and served as co-founder & CTO of Inphi, a pioneer in high-speed semiconductor interconnect technologies. He also served as CEO & co-founder of Eta Compute, an edge AI semiconductor company, and continues to advise emerging technology companies on strategy and commercialization. Raghavan's experience building innovative semiconductor businesses, leading engineering organizations, and commercializing advanced technologies are expected to provide valuable strategic guidance as Palomino expands its AI interconnect platform.
Executive commentary
“We are building a world-class leadership team and Strategic Advisory Board with deep expertise across AI infrastructure, semiconductor architecture, networking, and product innovation,” says Palomino’s co-founder & CEO Jeffrey B. Shealy. “Together, this exceptional team significantly strengthens our ability to execute our vision of becoming a premier AI interconnect company delivering differentiated semiconductor technologies that enable the next generation of AI infrastructure,” he adds.
“The future of AI infrastructure will require innovation across system architecture, silicon, networking, and advanced interconnect technologies,” says Gopalakrishnan. “Bringing together the complementary capabilities of Palomino and Vega Links creates an outstanding opportunity to develop next-generation AI interconnect solutions,” he adds. “Our objective is to develop highly differentiated AI interconnect chipsets that improve bandwidth, latency, power efficiency, and scalability while enabling customers to build larger and more efficient AI computing clusters.”
Industry opportunity
Palomino believes that future AI clusters will rely on heterogeneous interconnect technologies rather than a single approach. Copper is expected to remain important for very-short-reach applications, while optical technologies, including micro-VCSEL and micro-LED-based solutions, are expected to play an increasingly important role as AI clusters continue to scale. Palomino believes that this broader technology portfolio positions it to pursue opportunities across multiple segments of the rapidly expanding AI networking market.
The firm intends to leverage the combined engineering organization to accelerate customer engagements, expand strategic partnerships, and advance commercialization of its AI interconnect chipset roadmap.
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