News: Optoelectronics
13 November 2025
Tower extends 300mm wafer bonding technology across SiPho and SiGe BiCMOS
Specialty analog foundry Tower Semiconductor Ltd of Migdal Haemek, Israel has announced the expansion of its existing, mature 300mm wafer bonding technology (originally developed and in mass production for stacked BSI image sensors) to enable heterogeneous 3D-IC integration across its silicon photonics (SiPho) and silicon germanium (SiGe) BiCMOS processes, including full support by Cadence design tools for the stacked platform technology. The new offering is said to represent a step forward in extending wafer-scale 3D integration, requiring simultaneous use of multiple process design kits (PDKs), to new domains beyond image sensing, addressing the growing market demand for compact, high-performance systems for data-center applications.
Building on years of high-volume stacked sensor production on 200mm and 300mm wafers, Tower’s wafer bonding technology enables stacking wafers (for example, SiPho (PIC, photonic IC) and SiGe (EIC, electronic IC)) to create fully integrated 3D-ICs at the wafer scale. This capability integrates application-specific functions from different process technologies into a single high-density chip, delivering greater functionality and performance in a smaller form factor. This wafer-scale 3D-IC technology supports emerging applications such as co-packaged optics (CPO), which combines PICs and EICs, where compact, high-performance integration is essential.
“Our long-standing experience in high-volume wafer stacking for CIS technologies has laid the foundation for this next stage of 3D integration,” says Tower’s president Dr Marco Racanelli. “With our advanced 300mm wafer bonding process now supporting multiple wafer technologies on a single 3D-IC, we are enabling customers to achieve new levels of performance, functionality and integration density needed for CPO.”
Tower has already demonstrated the wafer bonding process’s precision alignment and reliability. Complementing the process technology, Tower has collaborated with Cadence Design Systems to extend their Virtuoso Studio Heterogeneous Integration flow, which allows co-simulation and co-verification of multiple process technologies within a unified design environment. This enhanced design enablement capability is now available for customers to use as a reference flow.
“Tower Semiconductor and Cadence have joined forces to provide a comprehensive design flow for multi-technology stacked die,” says Dr Samir Chaudhry, Tower’s VP of customer design enablement. “This enables designers to lay out, check connectivity, and fully simulate 3D-IC and wafer-bonded chips built from multiple technology platforms, all within a single Cadence design project. Compatible with Tower Semiconductor SiGe BiCMOS and SiPho PDKs, the new 3D-IC design flow is now fully supported by both companies, greatly improving first-pass success on complex multi-technology die projects,” he adds.
“Cadence and Tower have successfully collaborated for over two decades, helping our mutual analog IC customers achieve first-pass success with their complex designs,” says Ashutosh Mauskar, VP product management for the Custom Design and System Design and Analysis products at Cadence. “The validation of the Heterogeneous Integration flow, which supports die-to-wafer and wafer-to-wafer applications for PIC/EIC sub-systems using Tower technology, means our mutual customers can count on a robust and unified technology flow to help them deliver quality products on time.”
Tower reckons that this expansion reinforces its role in 3D-IC and heterogeneous integration, delivering advanced analog solutions that accelerate innovation across next-generation markets.
Tower releases 300mm silicon photonics process as standard foundry offering
