News: Microelectronics
11 December 2023
Intel demos first 3D stacked CMOS transistors combined with backside power and direct backside contact
At the 69th annual IEEE International Electron Devices Meeting (IEDM 2023) in San Francisco (9–13 December), Intel of Santa Clara, CA, USA showcased first-of-a-kind advances in 3D stacked CMOS (complementary metal oxide semiconductor) transistors combined with backside power and direct backside contacts. The firm also reported on scaling paths for recent R&D breakthroughs for backside power delivery, such as backside contacts, and it was the first to demonstrate successful large-scale 3D monolithic integration of silicon transistors with gallium nitride (GaN) transistors on the same 300mm wafer, rather than on package.
“As we enter the Angstrom era and look beyond five nodes in four years, continued innovation is more critical than ever,” Sanjay Natarajan, Intel senior VP & general manager of Components Research. “At IEDM 2023, Intel showcases its progress with research advancements that fuel Moore’s Law, underscoring our ability to bring leading-edge technologies that enable further scaling and efficient power delivery for the next generation of mobile computing.”
Transistor scaling and backside power are key to helping meet the exponentially increasing demand for more powerful computing, says Intel. The firm’s Components Research group has been stacking transistors, taking backside power to the next level to enable more transistor scaling and improved performance, as well as demonstrating that transistors made of different materials can be integrated on the same wafer.
Recent process technology roadmap announcements highlighting the company’s continued scaling – including PowerVia backside power, glass substrates for advanced packaging and Foveros Direct – originated in Components Research and are expected to be in production this decade.
At IEDM 2023, Components Research demonstrated new ways of putting more transistors on silicon while achieving higher performance. Researchers have identified key R&D areas necessary to continue scaling by efficiently stacking transistors. Combined with backside power and backside contacts, these present major steps forward in transistor architecture technology, Intel says. Along with improving backside power delivery and employing novel 2D channel materials, Intel is aiming to extend Moore’s Law to a trillion transistors on a package by 2030.
Intel’s latest transistor research presented at IEDM shows the industry-first ability to vertically stack complementary field-effect transistors (CFET) at a scaled gate pitch down to 60nm. This allows area efficiency and performance benefits by stacking transistors. It is also combined with backside power and direct backside contacts. Intel reckons that this underscores its leadership in gate-all-around (GAA) transistors and showcases its ability to innovate beyond RibbonFET.
Intel says that its technology development roadmap goes beyond five nodes in four years and identifies key R&D areas needed to continue transistor scaling with backside power delivery.
Intel’s PowerVia will be manufacturing-ready in 2024, which will be the first implementation of backside power delivery. At IEDM, Components Research identified paths to extend and scale backside power delivery beyond PowerVia, and the key process advances required to enable them. In addition, this work also highlighted the use of backside contacts and other novel vertical interconnects to enable area-efficient device stacking.
Also, Intel claims to be first to successfully integrate silicon transistors with GaN transistors on the same 300mm wafer and demonstrate that they performs well.
At IEDM 2022, Intel focused on performance enhancements and building a viable path to 300mm GaN-on-silicon wafers. This year, it is making advancements in process integration of silicon and GaN. Intel has now demonstrated a high-performance, large-scale integrated circuit solution – called DrGaN – for power delivery. Intel has demonstrated that this technology performs well and can potentially enable power delivery solutions to keep pace with the power density and efficiency demands of future computing.
Intel has also advanced its R&D in the 2D transistor space for future Moore’s Law scaling. Transition-metal dichalcogenide (TMD) 2D channel materials offer a unique opportunity to scale the transistor’s physical gate length below 10nm. At IEDM 2023, Intel demonstrated prototypes of high-mobility TMD transistors for both NMOS (n-channel metal oxide semiconductor) and PMOS (p-channel metal oxide semiconductor), the key components of CMOS. Intel also presented what is claimed to be the first gate-all-around (GAA) 2D TMD PMOS transistor, and the first 2D PMOS transistor fabricated on a 300mm wafer.
