CLICK HERE: free registration for Semiconductor Today and Semiconductor Today ASIACLICK HERE: free registration for Semiconductor Today and Semiconductor Today ASIA

20 February 2013

Poongsan partners with SEMATECH to develop high-pressure anneal processes for advanced silicon and non-Si devices

SEMATECH of Albany, NY, USA (the international research consortium of semiconductor device, equipment, and mterials manufacturers) says that South Korean annealing furnace manufacturer Poongsan has joined its Front End Processes (FEP) program, and will work with it to explore high-pressure anneal (HPA) techniques for silicon and non-silicon channel materials to improve device performance and reliability for next-generation technologies.

The solid-state device community is currently investigating non-silicon, high-mobility materials to increase carrier mobility within the device channels and improve overall transistor performance, says SEMATECH. High-mobility channels such as germanium and III-V compounds have the potential to operate at high speeds with low operating power and may be used in mainstream semiconductor CMOS technologies in the future. However, many manufacturing challenges associated with high-mobility channels (such as processes, tools, device test structures and environment, safety and health issues) need to be addressed before these materials-based solutions are brought to manufacturing.

Since 2006, Poongsan and SEMATECH have partnered in tool and process development projects that have demonstrated the technical merits of a high-pressure annealing furnace.

“Working with SEMATECH, we have demonstrated that high-pressure anneals are both effective and manufacturing-worthy approaches to high-k/Si interface defect passivation,” says Poongsan’s director of sales & marketing Dr Bob Wu. “From this work, we have gone on to develop and ship production-worthy annealing furnace tools to worldwide customers,” he adds. “We look forward to continuing our strategic partnership with SEMATECH as we work toward developing emerging technologies and improving products.”

As a member of SEMATECH’s FEP program, located at the College of Nanoscale Science and Engineering (CNSE) of the University at Albany (State University of New York), Poongsan will collaborate with SEMATECH’s engineers and leverage the consortium’s activities in advanced test structures, advanced materials and device electrical characterization to improve processing technologies in order to increase mobility and reduce interfacial defects. Specifically, SEMATECH and Poongsan will collaborate on the passivation of silicon and non-silicon gate stacks and other interfaces.

“To achieve better device performance and help shape the next generations of nanoelectronics, it’s necessary to partner to share know-how in materials, processing, equipment development and device technologies,” says Paul Kirsch, SEMATECH’s director of Front End Processes. “Poongsan’s proven expertise in high-pressure annealing processes will complement our own device and process expertise,” he adds. “We will work together on the technical and manufacturing gaps to address the continued scaling needs of today’s aggressive chip manufacturing market.”

The goal of SEMATECH’s FEP program is to provide novel leading-edge materials, processes, structural modules and electrical and physical characterization methods to support the continued scaling of logic and memory applications.




See Latest IssueRSS Feed

This site uses some harmless cookies in order to function click here to view our Cookie and Privacy Policy