Temescal

Semigas

CLICK HERE: free registration for Semiconductor Today and Semiconductor Today ASIACLICK HERE: free registration for Semiconductor Today and Semiconductor Today ASIA

Join our LinkedIn group!

Follow ST on Twitter

IQE

20 September 2018

DSFP transceiver MSA releases Hardware Specification Rev. 1.0

© Semiconductor Today Magazine / Juno PublishiPicture: Disco’s DAL7440 KABRA laser saw.

The DSFP (dual small-form-factor pluggable) MSA (multi-source agreement) Group has released the Rev. 1.0 Hardware Specification for the DSFP form-factor module (published on its website on 12 September).

The DSFP MSA’s founding member companies (Amphenol, Finisar, Huawei, Lumentum, Molex, NEC, TE Connectivity and Yamaichi) say they have addressed the technical challenges of doubling the SFP module density in the same footprint, while ensuring mechanical and electrical interoperability for optical transceivers produced by different manufacturers. DSFP networking equipment will also interoperate with existing SFP modules and cables.

DSFP Hardware Specification Rev. 1.0 includes complete electrical, mechanical and thermal specifications for the module and host card, including connector, cage, power and hardware I/O. Also included are operating parameters, data rates, protocols and supported applications.

The DSFP MSA Group is now developing the DSFP MIS (Management Interface Specification), which is an abridged version of the CMIS (Common MIS) being developed by the QSFP-DD, OSFP and COBO Advisors Group.

To address the growing port density and scalability requirements of wireless and 5G mobile infrastructure, the DSFP specification doubles the data rate and port density of SFP modules. SFP has a single electrical lane pair operating at bit and data rates up to 28Gbps using NRZ (non-return to zero) modulation and 56Gbps using PAM4 (four-level pulse amplitude modulation). DSFP has two electrical lane pairs, each operating at bit rates up to 28Gbps using NRZ and 56Gbps using PAM4, supporting aggregate date rates up to 56Gbps and 112Gbps, respectively. DSFP will potentially scale to a per lane bit rate of 112Gbps using PAM4, supporting aggregate data rate up to 224Gbps. SFP modules can be plugged into DSFP ports for backwards compatibility.

The new DSFP MSA form factor will “double interface bandwidth and port density while maintaining compatibility with the existing SFP family of optics,” says Zhoujian Li, president of R&D, Wireless Networks, at Huawei. “The DSFP form factor is low cost, has excellent high-speed signal integrity, reduces PCB area and is easy to design and manufacture. It is a great platform that enables 5G deployment and evolution, while fully protecting our customers’ investment,” he adds.

“Publication of the DSFP Hardware Specification is part of an industry trend of quickly developing solutions optimized for specific applications. Stringent cost, power and size constraints in demanding market segments, like mobile infrastructure, leads to solutions focused strictly on required functionality,” comments DSFP MSA Group chair Chris Cole, Finisar’s VP of advanced development.

“TE works closely with our customers and end-equipment operators to understand their requirements and meet the market needs,” says Nathan Tracy, technologist at TE Connectivity and manager of industry standards. “The new DSFP form factor provides a method to double data rate and channel density using the well-established SFP mechanical geometry as a starting point,” he adds.

“There is tremendous industry pull for higher speeds and densities on switches and servers, while maintaining backwards compatibility. The DSFP form factor achieves this by doubling the number of high-speed lanes in the same size package as SFP,” says Amphenol’s technical business development manager Greg McSorley.

Tags: SFP

Visit: www.dsfpmsa.org

Share/Save/Bookmark
See Latest IssueRSS Feed

AXT