Temescal

Semigas

CLICK HERE: free registration for Semiconductor Today and Semiconductor Today ASIACLICK HERE: free registration for Semiconductor Today and Semiconductor Today ASIA

Join our LinkedIn group!

Follow ST on Twitter

IQE

10 July 2018

SILTECTRA reports application of COLD SPLIT wafer thinning technology to GaAs

© Semiconductor Today Magazine / Juno PublishiPicture: Disco’s DAL7440 KABRA laser saw.

At the SEMICON West 2018 tradeshow and conference in San Francisco (10-12 July), wafering technology firm SILTECTRA GmbH of Dresden, Germany has revealed new enabling and cost-of-ownership (CoO) advantages for its COLD SPLIT laser-based wafer thinning technology. Collectively, the benefits aim to further enable manufacturers of power semiconductors.

Enabling wafering solution for diverse materials

In the latest demonstration of COLD SPLIT’s capabilities, SILTECTRA says that, when applied to gallium arsenide (GaAs), COLD SPLIT achieved the same thinness and near-zero material loss as previously shown for silicon carbide (SiC), gallium nitride (GaN), sapphire and silicon.

The data comes from a recent study (funded by the State Government of Saxony) to establish if COLD SPLIT could achieve full crack propagation across the laser plane when applied to GaAs. Participants included a leading materials supplier and a renowned laser institute, as well as SILTECTRA. The results validated COLD SPLIT as a high-performance thinning solution for GaAs and demonstrated that the technique can thin a range of diverse materials with complex properties.

Cost-of-ownership benefits for SiC-based devices

The data builds on feedback from COLD SPLIT customers who found that the novel thinning technique is demonstrating strong CoO advantages compared with traditional grinding. Not only can COLD SPLIT thin wafers to 50μm and below in minutes, it produces virtually no material loss. Grinding is a slower process and can incur material waste of up to 90%. Now, due to the adaptation of ‘twinning’, COLD SPLIT users can reclaim substrate material generated (and previously wasted) during backside grinding and create a fully optimizable bonus wafer. SILTECTRA believes that these benefits can cut consumables costs by 50% and reduce overall wafering costs by as much as 30%.

“Significantly lower consumables costs are a key driver of COLD SPLIT’s compelling CoO, especially for SiC-based devices,” says chief technology officer Dr Jan Richter. “While the industry is starting to adopt SiC for power semiconductors, it is an extraordinarily hard substance. Every single micron must be ground and polished, micron-by-micron. Grinding involves expensive diamond-based consumables, and when coupled with the technique’s inherent material waste, costs can be high,” he adds. “In contrast, COLD SPLIT produces almost no waste, which vastly reduces consumables costs. And because the technique can save virtually every micron of SiC and turn surplus material into a bonus wafer, CoO is further boosted.”

Potential electrical performance improvement for power semiconductors

The new data may also have performance implications for end-user devices. “Take low-voltage SiC-based Schottky diodes, for example,” says CEO Dr Harald Binder. “With these diodes, low resistance is essential to reducing electrical losses in end-user applications. The thickness of the final device influences resistance. The thinner the device, the lower the resistance. Reducing thickness, therefore, can decrease resistance and reduce electrical losses. This means that, in addition to low-cost/high-speed wafer thinning, COLD SPLIT can potentially also improve the electrical performance of low-voltage devices,” he adds.

“Much of our new data is occurring in real time as the industry shifts fast to new materials. That said, the innovation has been happening at SILTECTRA for many years and is protected by 70 patent families covering technology, manufacturing equipment, materials and expertise,” Binder continues. “It is gratifying to see our discoveries exceeding even their original promise as we collaborate with manufacturers to help them achieve aggressive roadmap goals.”

See related items:

Siltectra’s new patents extend SiC process to split substrates with sub-100μm material loss

SILTECTRA validates twinned SiC wafer produced using COLD SPLIT laser-based wafer thinning technique

Tags: GaAs substrates

Visit: www.SILTECTRA.com

Share/Save/Bookmark
See Latest IssueRSS Feed

AXT