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3 September 2014

POET collaborating with foundry to reproduce and enhance repeatability at 100nm

POET Technologies Inc of Toronto, Canada – which, through subsidiary OPEL Defense Integrated Systems (ODIS Inc) of Storrs, CT, USA, has developed the proprietary planar-optoelectronic technology (POET) platform for monolithic fabrication of integrated III-V-based electronic and optical devices on a single semiconductor wafer – has announced an agreement with a third-party foundry to reproduce and enhance repeatability of the 100nm scale results obtained at the POET labs at the University of Connecticut (UCONN). The third-party foundry will also assist the POET team in shrinking the 100nm Planar Electrical Technology (PET) devices and process to a 40nm feature size.

Having developed a structure suitable for scaling its transistors to 100nm, POET has engaged a third-party foundry to replicate the results with greater precision and larger scale using electron-beam writing tools. Definition and repeatability of 100nm has been difficult in the POET labs due to the limitations of available lithography tools and other equipment. The collaboration gives the team access to superior capability and diagnostics, allowing the POET approach to start to scale to both 3” and 6” wafers with much larger device count and across-wafer alignment. The fine features will then be merged with optical lithography and other procedures necessary to transition to a manufacturing environment. In addition, the effort will target line-width reductions from 100nm down to 40nm which should enable POET performance parameters to compete with present state-of-the-art processes. The reduction will be parallel to the firm’s efforts with its Synopsys TCAD collaboration.

“Developing the 100nm feature size technology in the current POET labs has proven to be challenging,” notes chief scientist and board member Dr Geoff Taylor. “With the collaboration of our third-party foundry, we now have access to state-of-the-art equipment... This will help us make the process more stable and predictable and help prove our process in a true manufacturing environment.”

This announcement acompanies the announcement regarding collaboration with Synopsys Inc (which provides software, IP and services used to accelerate innovation in chips and electronic systems) and the creation of POET’s first process design kit (PDK). The collaboration will see the development of an advanced model of PET devices targeting a 40nm technology node, a significant production node of highly integrated systems-on-chip (SoC) silicon CMOS device. The results of the physical devices at 40nm developed at the third-party foundry can then be correlated to the models of the PET technology developed using TCAD tools from Synopsys and vice-versa.

“We have the right collaboration in place with Synopsys and our third-party foundry to model our technology down to 40nm and correlate our process to real physical device measurements,” believes executive chairman interim CEO Peter Copetti. “This should provide us with results needed to showcase our technology to potential customers at the optimum node for our platform. We expect synergistic benefits from having parallel operations with the same end target.”

See related items:

Synopsys to develop advanced model and first PDK of POET’s planar electronic technology

POET provides update on 100nm initiative, process equipment upgrade, and technology design kits

Tags: POET

Visit: www.poet-technologies.com

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