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11 July 2014

FinScale launches 3D MOSFET architecture and process for licensing and technology transfer

FinScale Inc of Livermore, CA, USA, which develops and licenses device and process innovations for the semiconductor industry, has announced availability of its qFinFET technology, a next-generation 3D MOSFET architecture and manufacturable process transferable to foundries and integrated device manufacturers (IDMs).

FinScale claims that, crafted from a combination of many unique device and process innovations, qFinFET technology offers improvements in performance, power efficiency and circuit density, along with substantially lower leakage, parametric variability and manufacturing costs than available advanced-node FinFET and planar technology alternatives. From a device design optimized for quantum effects, ballistic transport and the nano-material properties of silicon, the quantum FinFET device architecture is intended to scale to the end of the silicon MOSFET era.

“The technology shift from planar to 3D device architectures has opened new degrees of freedom and exciting opportunities for new innovations,” says George Cheroff, an IBM Research manager and semiconductor pioneer who envisioned and developed the first n-channel planar MOSFET process used for memory and logic circuits in computers. “The qFinFET technology elegantly combines the advantages of current FinFET and planar FD-SOI technologies, and mitigates their inherent weaknesses to provide a unifying platform that will put the semiconductor industry back on track with Moore’s Law,” he reckons.

“qFinFET offers manufacturers a high-yield 3D process for building scalable aspect-ratio fins that can be formed without double patterning down to the 14/16nm node, and provide increased performance and transistor width (W) per unit area,” says president & chief executive officer Jeffrey Wolf. “Resulting fin transistor topologies deliver additional area reductions, and offer designers further area-saving and performance-boosting opportunities to differentiate at the cell library and circuit level when integrated with leading middle-of-line (MOL) technologies,” he adds.

“We conceived the Quantum FinFET by pushing silicon to its quantum scaling limits, while seeking to maximize carrier mobility, electrostatic gate control, yield and reliability,” says chief technology officer Dr Victor Koldyaev. “Using this approach we designed the qFinFET front-end-of-line (FEOL) device and process solution for the 7nm and 10nm generations, and were pleased that the same device concept would significantly boost parametric performance and economic returns for manufacturers back to the 28/32nm node. We then laid out standard cells, SRAMs, eDRAMs and 2-bit/cell non-volatile memories using industry standard design rules and realized that we could readily exceed the best published results at those nodes and give manufacturers and designers opportunities for further improvement.”

FinScale reckons that qFinFET technology offers unique benefits for foundries and IDMs. The included high-density and high-performance logic and memory configurations, along with inherent low-noise analog/RF device characteristics, make qFinFET a robust SoC platform, either on bulk or silicon-on-insulator (SOI) substrates. Standalone DRAM, flash and SRAM memory designers and manufacturers can configure the included bit cells into dense arrays, and build dense, highly reliable sense amplifiers and low-leakage pass transistors.

FinScale presented its qFinFET technology on 8 July at the Silicon Innovation Forum of the SEMICON West 2014 event in San Francisco.

Tags: FinFETs

Visit: www.finscale.com

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