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7 July 2014

CNSE/SUNYIT presenting R&D plans for III-V and beyond-III-V materials for sub-10nm transistors

At the SEMICON West 2014 conference in San Francisco (8-10 July), researchers from the newly merged State University of New York (SUNY) College of Nanoscale Science and Engineering (CNSE)/SUNY Institute of Technology (SUNYIT) in Albany, NY, USA, in addition to scientists from global corporate partners including Applied Materials, ASML, GLOBALFOUNDRIES, IBM, Intel, KLA-Tencor, Nikon Precision, Samsung, SEMATECH, Tokyo Electron and TSMC, are taking part in presentations and informational sessions on the advancement of semiconductor-based R&D — including innovations paving the way for the transition to the industry’s new 450mm wafer standard.

Also, presenters will detail the four newly formed technology development centers based at the Albany Nanotech Complex, which will be jointly managed by CNSE/SUNYIT and SEMATECH. The centers will focus on chemical mechanical polishing/planarization (CMP), 3D (computer chip packaging), resist, and III-V compounds, enabling companies to assess their materials, test new tooling, and validate designs through access to CNSE/SUNYIT’s fabrication facilities and engineering know-how, in addition to SEMATECH’s network of consortium members.

Presentations by CNSE/SUNYIT researchers and corporate partners will provide industry updates, specifically detailing progress made by the G450C (Global 450mm Consortium). Presentation topics include ‘450mm Lithography’, ‘450mm Notchless Wafer Update’, ‘G450C Technology Development Program Status’, ‘450mm Transition Status and Briefing’, ‘Readiness of Advanced Lithography Technologies for High-Volume Manufacturing’, ‘Chemical Mechanical Polishing Market Trends and Technology Advances’, ‘Sustainable Manufacturing Forum: Next Generation Eco Fab’, and ‘Driving Transistor Technology Sub-10nm: Process and Equipment Directions’.

Specifically, in ‘Driving Transistor Technology Sub-10nm: Process and Equipment Directions’ on 9 July, CNSE researchers are presenting their development focus on materials beyond silicon. III-V layers are being evaluated as channel materials for next-generation devices. CNSE has established an ecosystem for collaborative III-V work with industrial and research partner institutions, and is developing modules for III-V gate stack, contact and source-drain engineering that are compliant with environmental guidelines while driving to device performance targets.

Beyond III-V, CNSE is working with partners from academia, industry and federal research programs on the growth, device design and integrated module development for 2D materials layers with a view to their subsequent introduction into mainstream processing. Initial successes have been made in graphene growth and transfer onto 300mm wafer substrates for clean, repeatable processing through the CNSE development facility.

Tags:  CNSE

Visit: www.sunycnse.com/Outreach/SEMICONWest2014.aspx

Visit: www.sunycnse.com

Visit: www.sunyit.edu

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