Temescal

Semigas

CLICK HERE: free registration for Semiconductor Today and Semiconductor Today ASIACLICK HERE: free registration for Semiconductor Today and Semiconductor Today ASIA

Join our LinkedIn group!

Follow ST on Twitter

IQE

12 December 2013

Imec demos first strained germanium FinFETs at IEDM

At the IEEE International Electron Devices Meeting (IEDM 2013) in Washington D.C., USA (9-11 December), nanoelectronics research institute imec of Leuven, Belgium reported the first functional strained germanium (Ge) quantum-well channel pMOS FinFET transistors, fabricated with a silicon fin replacement process on 300mm silicon wafers. The device shows a possible evolution of the FinFET/trigate architecture for 7nm and 5nm CMOS technologies.

Since the 90nm technology node, an embedded silicon germanium (SiGe) source/drain has been a popular stressor method to produce strained silicon that enhances pMOS devices. With diminishing device dimensions, the volume to implement stressors in the source and drain has also been severely scaled. In particular, with thin-body devices like FinFETs, the difficulty is even more pronounced. A possible relief would be to implement highly strained material directly into the channel itself.

Imec’s solution - growing compressively strained Ge-channels on a relaxed SiGe buffer - has already proven to boost the channel mobility, and is also known for its excellent scalability potential. The use of a fin replacement process to fabricate the strained Ge channel device makes it especially attractive for co-integration with other devices on a common silicon substrate. The reported strained Ge p-channel FinFETs on SiGe trench buffer achieved peak transconductance (gmSAT) values of 1.3mS/┬Ám at VDS=-0.5V with good short-channel control down to 60nm gate length. The transconductance-to-subthreshold slope ratio of the devices (gmSAT/SSSAT)is high compared to published relaxed Ge FinFET devices.

Future developments will focus on improving the device performance through P-doping in the SiGe, optimizing silicon cap passivation thickness on the Ge, and improving the gate wrap of the channel. “Unlike published Ge FinFETs, this work demonstrates a Ge-SiGe heterostructure-based quantum-well device in a FinFET form, which not only provides strain benefits but also enhances short-channel control,” notes Nadine Collaert, program manager of the Ge/IIIV device R&D.

“Just recently, we reported the implementation of IIIV material into the device architecture using a fin replacement process,” says Aaron Thean, director of the logic R&D program at imec. “This new achievement - implementing Ge into the channel through our fin replacement process - is another key ingredient to our menu of process possibilities for monolithic heterogeneous integration to extend CMOS and SOCs [system-on-chip devices].”

Imec’s research into next-generation FinFETs is part of imec’s core CMOS program, in cooperation with the institute’s key partners including Intel, Samsung, TSMC, Globalfoundries, Micron, SK Hynix, Toshiba/Sandisk, Panasonic, Sony, Qualcomm, Altera, Fujitsu, nVidia and Xilinx.

See related items:

Imec demos first III-V FinFET devices monolithically integrated on 300mm silicon

Tags: FinFETs III-V CMOS

Visit: www.imec.be

Share/Save/Bookmark
See Latest IssueRSS Feed

AXT